The disclosure relates to correction circuits, and in particular, to correction circuits for successive-approximation-register analog-to-digital converters.
Unless otherwise indicated herein, the approaches described in this section are not admitted to be prior art by inclusion in this section.
High frequency buck converters have very short high side on-times, so that often less than 10 nanoseconds is provided to measure current across the high side field effect transistor (FET) of the switching driver, thereby making the use of traditional current sense amplifiers ineffective. Often a replica FET is used to measure current in the power FET. The replica FET has a reference current that sets up a current density identical to that in the power FET at current limit and the differential drain-source voltage Vds across this replica FET is buffered and differentially applied to a digital-to-analog (DAC) in a successive-approximation-register (SAR) analog-to-digital converter (ADC) as its full scale reference. The input to the SAR ADC is the Vds voltage across the power FET as an indication of the current. However, the on-resistance Ron of the power FET is not linear. Even with a constant gate-source voltage Vgs, the on-resistance Ron of the FET varies with Vds.
The ADC can only compensate for Vds non-linearity for currents near the current limit. At currents less than the current limit, the ADC reports current values much lower than the actual currents in the power FET. These errors can approach 15% and when added to the other system errors quickly make the tolerance of the ADC quite poor.